[PATCH 009/106] ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV_MASK
Luis Henriques
luis.henriques at canonical.com
Tue Jul 30 09:30:28 UTC 2013
3.5.7.18 -stable review patch. If anyone has any objections, please let me know.
------------------
From: Fabio Estevam <fabio.estevam at freescale.com>
commit 5c78dfe87ea04b501ee000a7f03b9432ac9d008c upstream.
SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of
register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range.
Reported-by: Oskar Schirmer <oskar at scara.com>
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Mark Brown <broonie at linaro.org>
Signed-off-by: Luis Henriques <luis.henriques at canonical.com>
---
sound/soc/codecs/sgtl5000.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h
index 8a9f435..d3a68bb 100644
--- a/sound/soc/codecs/sgtl5000.h
+++ b/sound/soc/codecs/sgtl5000.h
@@ -347,7 +347,7 @@
#define SGTL5000_PLL_INT_DIV_MASK 0xf800
#define SGTL5000_PLL_INT_DIV_SHIFT 11
#define SGTL5000_PLL_INT_DIV_WIDTH 5
-#define SGTL5000_PLL_FRAC_DIV_MASK 0x0700
+#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff
#define SGTL5000_PLL_FRAC_DIV_SHIFT 0
#define SGTL5000_PLL_FRAC_DIV_WIDTH 11
--
1.8.3.2
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