[PATCH 5/5] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

[Luis Henriques]

From: Jesse Barnes <jbarnes at virtuousgeek.org>

BugLink: http://bugs.launchpad.net/bugs/1140716

"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa at intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
(cherry picked from commit 3ac7831314eba873d60b58718123c503f6961337)

Signed-off-by: Luis Henriques <luis.henriques at canonical.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 32b2458..c3654ff 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -229,7 +229,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
-		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 	}
 
 	ret = intel_ring_begin(ring, 4);
-- 
1.8.1.2