Fwd: [PATCH v2] x86 intel power: Initialize MSR_IA32_ENERGY_PERF_BIAS

Tim Gardner tim.gardner at canonical.com
Thu Jul 14 17:40:05 UTC 2011


We should watch for this to appear in Oneiric stable, then propose an 
SRU for Natty as it is quite applicable (and is a clean cherry-pick so far)

rtg

-------- Original Message --------
Subject: [PATCH v2] x86 intel power: Initialize MSR_IA32_ENERGY_PERF_BIAS
Date: Thu, 14 Jul 2011 00:53:24 -0400 (EDT)
From: Len Brown <lenb at kernel.org>
To: H. Peter Anvin <hpa at zytor.com>
CC: Linus Torvalds <torvalds at linux-foundation.org>,	Ingo Molnar 
<mingo at elte.hu>, x86 at kernel.org,	linux-pm at lists.linux-foundation.org, 
linux-kernel at vger.kernel.org,	Thomas Gleixner <tglx at linutronix.de>,	Alan 
Cox <alan at lxorguk.ukuu.org.uk>,	Andrew Morton 
<akpm at linux-foundation.org>,	Arjan van de Ven <arjan at infradead.org>

From: Len Brown <len.brown at intel.com>

Since 2.6.36 (23016bf0d25), Linux prints the existence of "epb" in 
/proc/cpuinfo,
Since 2.6.38 (d5532ee7b40), the x86_energy_perf_policy(8) utility has
been available in-tree to update MSR_IA32_ENERGY_PERF_BIAS.

However, the typical BIOS fails to initialize the MSR, presumably
because this is handled by high-volume shrink-wrap operating systems...

Linux distros, on the other hand, do not yet invoke 
x86_energy_perf_policy(8).
As a result, WSM-EP, SNB, and later hardware from Intel will run in its
default hardware power-on state (performance), which assumes that users
care for performance at all costs and not for energy efficiency.
While that is fine for performance benchmarks, the hardware's intended 
default
operating point is "normal" mode...

Initialize the MSR to the "normal" by default during kernel boot.

x86_energy_perf_policy(8) is available to change the default after boot,
should the user have a different preference.

cc: stable at kernel.org
Signed-off-by: Len Brown <len.brown at intel.com>
---
  arch/x86/include/asm/msr-index.h |    3 +++
  arch/x86/kernel/cpu/intel.c      |   18 ++++++++++++++++++
  2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h 
b/arch/x86/include/asm/msr-index.h
index 43a18c7..91fedd9 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -250,6 +250,9 @@
  #define MSR_IA32_TEMPERATURE_TARGET	0x000001a2

  #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE	0
+#define ENERGY_PERF_BIAS_NORMAL		6
+#define ENERGY_PERF_BIAS_POWERSWAVE	15

  #define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index d16c2c5..7c1ca07 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -448,6 +448,24 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)

  	if (cpu_has(c, X86_FEATURE_VMX))
  		detect_vmx_virtcap(c);
+
+	/*
+	 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
+	 * x86_energy_perf_policy(8) is available to change it at run-time
+	 */
+	if (cpu_has(c, X86_FEATURE_EPB)) {
+		u64 epb;
+
+		rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
+		if ((epb & 0xF) == 0) {
+			printk_once(KERN_WARNING, "x86: updated energy_perf_bias"
+				" to 'normal' from 'performance'\n"
+				"You can view and update epb via utility,"
+				" such as x86_energy_perf_policy(8)\n");
+			epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
+			wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
+		}
+	}
  }

  #ifdef CONFIG_X86_32
-- 
1.7.6.134.gcf13f


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