[Lucid][SRU] drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge

Zhao, Yingying yingying.zhao at intel.com
Fri May 7 06:40:19 UTC 2010

SRU Justification:
These two patches fix one important bug (https://bugs.freedesktop.org/show_bug.cgi?id=27108) about interrupt handling where reporters said "On some machines the Xserver freezes inside the intel driver in a ioctl (all output ceases) until the mouse is moved."
And from comments, this issue has only been seen on Ironlake gfx so far.

Test Cases:
>From bug reporter's comments:
Triggering the bug is extremely difficult, and seems to depend on weird
circumstances (I considered air pressure or state of the moon for a while). We
had one machine shipped to us that exposed the bug, when it arrived (it even
woke up from suspend, so it was in exactly the same state) we weren't able to
reproduce even on this machine. But colleagues we trust have seen the bug with
their very eyes.


commit e552eb7038a36d9b18860f525aa02875e313fe16
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date:   Wed Apr 21 11:39:23 2010 -0700

    drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge

    Since 965, the hardware has supported the PIPE_CONTROL command, which
    provides fine grained GPU cache flushing control.  On recent chipsets,
    this instruction is required for reliable interrupt and sequence number
    reporting in the driver.

    So add support for this instruction, including workarounds, on Ironlake
    and Sandy Bridge hardware.


    Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
    Tested-by: Chris Wilson <chris at chris-wilson.co.uk>
    Signed-off-by: Eric Anholt <eric at anholt.net>

commit 1918ad77f7f908ed67cf37c505c6ad4ac52f1ecf
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date:   Fri Apr 23 09:32:23 2010 -0700

    drm/i915: fix non-Ironlake 965 class crashes

    My PIPE_CONTROL fix (just sent via Eric's tree) was buggy; I was
    testing a whole set of patches together and missed a conversion to the
    new HAS_PIPE_CONTROL macro, which will cause breakage on non-Ironlake
    965 class chips.  Fortunately, the fix is trivial and has been tested.

    Be sure to use the HAS_PIPE_CONTROL macro in i915_get_gem_seqno, or
    we'll end up reading the wrong graphics memory, likely causing hangs,
    crashes, or worse.

    Reported-by: Zdenek Kabelac <zdenek.kabelac at gmail.com>
    Reported-by: Toralf Förster <toralf.foerster at gmx.de>
    Tested-by: Toralf Förster <toralf.foerster at gmx.de>
    Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
    Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>

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