[PATCH] ENGR00121057 switch low power mode only support in mc13892 2.0a

Amit Kucheria amit.kucheria at canonical.com
Wed Aug 11 11:56:43 UTC 2010


On 10 Aug 11, Stefan Bader wrote:
> On 08/11/2010 12:41 PM, Bryan Wu wrote:
> > On 08/10/2010 11:36 PM, Brad Figg wrote:
> >> On 08/10/2010 12:07 AM, Bryan Wu wrote:
> >>> From: Shen Yong<b00984 at freescale.com>
> >>>
> >>> switch low power mode will cause problems on previous version of
> >>> mc13892, which may break mc13892 chip.
> >>> This is a fix for ENGR00120510.
> >>>
> >>> BugLink: http://bugs.launchpad.net/bugs/615722
> >>>
> >>> Signed-off-by: Shen Yong<b00984 at freescale.com>
> >>> Signed-off-by: Bryan Wu<bryan.wu at canonical.com>
> >>> ---
> >>>   arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c |   30 +++++++++++++++--------
> >>>   1 files changed, 19 insertions(+), 11 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c
> >>> index e8a03cf..13869d0 100644
> >>> --- a/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c
> >>> +++ b/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c
> >>> @@ -346,17 +346,25 @@ static int mc13892_regulator_init(struct mc13892 *mc13892)
> >>>   	pmic_write_reg(REG_MODE_1, value, 0xffffff);
> >>>
> >>>   	/* enable switch audo mode */
> >>> -	pmic_read_reg(REG_SW_4,&value, 0xffffff);
> >>> -	register_mask = (SWMODE_MASK<<  SW1MODE_LSB) | (SWMODE_MASK<<  SW2MODE_LSB);
> >>> -	value&= ~register_mask;
> >>> -	value |= (SWMODE_AUTO<<  SW1MODE_LSB) | (SWMODE_AUTO<<  SW2MODE_LSB);
> >>> -	pmic_write_reg(REG_SW_4, value, 0xffffff);
> >>> -
> >>> -	pmic_read_reg(REG_SW_5,&value, 0xffffff);
> >>> -	register_mask = (SWMODE_MASK<<  SW3MODE_LSB) | (SWMODE_MASK<<  SW4MODE_LSB);
> >>> -	value&= ~register_mask;
> >>> -	value |= (SWMODE_AUTO<<  SW3MODE_LSB) | (SWMODE_AUTO<<  SW4MODE_LSB);
> >>> -	pmic_write_reg(REG_SW_5, value, 0xffffff);
> >>> +	pmic_read_reg(REG_IDENTIFICATION,&value, 0xffffff);
> >>> +	/* only for mc13892 2.0A */
> >>> +	if ((value&  0x0000FFFF) == 0x45d0) {
> >>> +		pmic_read_reg(REG_SW_4,&value, 0xffffff);
> >>> +		register_mask = (SWMODE_MASK<<  SW1MODE_LSB) |
> >>> +		       (SWMODE_MASK<<  SW2MODE_LSB);
> >>> +		value&= ~register_mask;
> >>> +		value |= (SWMODE_AUTO<<  SW1MODE_LSB) |
> >>> +			(SWMODE_AUTO<<  SW2MODE_LSB);
> >>> +		pmic_write_reg(REG_SW_4, value, 0xffffff);
> >>> +
> >>> +		pmic_read_reg(REG_SW_5,&value, 0xffffff);
> >>> +		register_mask = (SWMODE_MASK<<  SW3MODE_LSB) |
> >>> +			(SWMODE_MASK<<  SW4MODE_LSB);
> >>> +		value&= ~register_mask;
> >>> +		value |= (SWMODE_AUTO<<  SW3MODE_LSB) |
> >>> +			(SWMODE_AUTO<<  SW4MODE_LSB);
> >>> +		pmic_write_reg(REG_SW_5, value, 0xffffff);
> >>> +	}
> >>>
> >>>   	/* Enable coin cell charger */
> >>>   	value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
> >>
> >> Bryan,
> >>
> >> Do you have positive test results from testing this patch? We want to make sure
> >> this patch fixes the issue that we have been seeing.
> >>
> > 
> > Brad,
> > 
> > Yeah, it can be confirmed by Ranjani from Freescale. I copied him in this email
> > thread.
> > 
> > Thanks,
> 
> OK, so this sounds like we can take it. ACK

I think Bryan meant we should wait for confirmation from Ranjani. _She_ will
confirm if this fix doesn't brick BB2.5.

BTW, is there any chance of unbricking bricked BB2.5 (like mine)?

/Amit

-- 
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Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
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