[KARMIC ARM] UBUNTU: SAUCE: Fix USB and add some Babbage 2 support
Manoj Iyer
manoj.iyer at canonical.com
Sat Jul 18 15:20:04 UTC 2009
The patch is require to make USB work ont the babbage 2 board.
>From 7cbef01ec040369d230438bd48fc0c09abc7e8b8 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <Dinh.Nguyen at freescale.com>
Date: Sat, 18 Jul 2009 10:16:09 -0500
Subject: [PATCH] UBUNTU: SAUCE: Fix USB and add some Babbage 2 support
Signed-off-by: Manoj Iyer <manoj.iyer at canonical.com>
Author: Dinh Nguyen <Dinh.Nguyen at freescale.com>
---
arch/arm/mach-mx51/mx51_babbage_gpio.c | 290 ++++++++++++++++++++++++++--
arch/arm/plat-mxc/include/mach/hardware.h | 7 +-
2 files changed, 275 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-mx51/mx51_babbage_gpio.c b/arch/arm/mach-mx51/mx51_babbage_gpio.c
index f8d0364..bebebdc 100644
--- a/arch/arm/mach-mx51/mx51_babbage_gpio.c
+++ b/arch/arm/mach-mx51/mx51_babbage_gpio.c
@@ -103,26 +103,24 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
{
MX51_PIN_EIM_A23, IOMUX_CONFIG_GPIO,
},
+ /* USBH2_CLK */
{
MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2,
(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
},
+ /* USBH2_DIR */
{
MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2,
(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
},
+ /* USBH2_STP */
{
MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2,
(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
},
- {
- MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2,
- (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
- },
{ /*MDIO */
MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3,
(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_ENABLE |
@@ -158,9 +156,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO,
},
{
- MX51_PIN_EIM_CRE, IOMUX_CONFIG_GPIO,
- },
- {
MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1,
(PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
},
@@ -182,7 +177,7 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
},
{
MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO,
- (PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU),
+ PAD_CTL_100K_PU,
},
{
MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO,
@@ -229,6 +224,24 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
INPUT_CTL_PATH1,
},
+#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
+ { /* DISP2_DAT16 */
+ MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT5,
+ },
+ { /* DISP2_DAT17 */
+ MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT5,
+ },
+ {
+ MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4,
+ (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_HIGH |
+ PAD_CTL_SRE_FAST),
+ MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, INPUT_CTL_PATH1,
+ },
+#endif
+ {
+ MX51_PIN_NANDF_D12, IOMUX_CONFIG_GPIO,
+ 0,
+ },
{
MX51_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
0x1E4,
@@ -311,27 +324,33 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
},
{
MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
@@ -342,6 +361,47 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
(PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
},
{
+ MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+ (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ },
+ {
+ MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+ (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ },
+ {
+ MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0,
+ (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ },
+ {
+ MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0,
+ (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ },
+ {
+ MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0,
+ (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ },
+ {
+ MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0,
+ (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ },
+ {
+ MX51_PIN_GPIO1_4, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+ (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
+ },
+ {
+ MX51_PIN_GPIO1_5, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+ (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
+ },
+ {
+ MX51_PIN_GPIO1_6, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+ (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
+ },
+ { /* Detect pin GPIO BB2.0 and BB2.5 */
+ MX51_PIN_UART3_RXD, IOMUX_CONFIG_ALT3,
+ (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
+ },
+ {
MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0,
(PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
@@ -389,6 +449,11 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
PAD_CTL_100K_PU | PAD_CTL_HYS_NONE | PAD_CTL_DDR_INPUT_CMOS |
PAD_CTL_DRV_VOT_LOW),
},
+ {
+ MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0,
+ (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_SRE_FAST),
+ },
};
void __init mx51_babbage_io_init(void)
@@ -401,8 +466,8 @@ void __init mx51_babbage_io_init(void)
mxc_iomux_set_pad(MX51_PIN_GPIO1_7, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_GPIO1_7, 0);
- mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 1);
+ if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
/* Drive I2C1 SDA line low */
mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_3, PAD_CTL_DRV_HIGH |
@@ -417,16 +482,17 @@ void __init mx51_babbage_io_init(void)
mxc_set_gpio_direction(MX51_PIN_GPIO1_2, 0);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_2, 0);
+ msleep(5);
+ mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
+ }
+
/* USB HUB RESET - De-assert USB HUB RESET_N */
msleep(1);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 0);
- msleep(5);
+ msleep(1);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 1);
- msleep(5);
- mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
- mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
-
for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
mxc_request_iomux(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].mux_mode);
@@ -441,6 +507,13 @@ void __init mx51_babbage_io_init(void)
mxc_set_gpio_direction(MX51_PIN_GPIO1_8, 1);
mxc_set_gpio_direction(MX51_PIN_GPIO1_0, 1); /* SD1 CD */
mxc_set_gpio_direction(MX51_PIN_GPIO1_1, 1); /* SD1 WP */
+ if (board_is_babbage_2_5() == 1)
+ /* BB2.5 */
+ mxc_set_gpio_direction(MX51_PIN_GPIO1_6, 1); /* SD2 CD */
+ else
+ /* BB2.0 */
+ mxc_set_gpio_direction(MX51_PIN_GPIO1_4, 1); /* SD2 CD */
+ mxc_set_gpio_direction(MX51_PIN_GPIO1_5, 1); /* SD2 WP */
/* reset FEC PHY */
mxc_set_gpio_direction(MX51_PIN_EIM_A20, 0);
@@ -454,11 +527,186 @@ void __init mx51_babbage_io_init(void)
msleep(10);
mxc_set_gpio_dataout(MX51_PIN_EIM_A21, 1);
+ if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
/* MX51_PIN_EIM_CRE - De-assert USB PHY RESETB */
mxc_set_gpio_direction(MX51_PIN_EIM_CRE, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_CRE, 1);
+ /* hphone_det_b */
+ mxc_set_gpio_direction(MX51_PIN_NANDF_CS0, 1);
+ } else {
+ mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
+ mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);
+ mxc_free_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+
+ /* i2c1 SDA */
+ mxc_request_iomux(MX51_PIN_EIM_D16,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH1);
+ mxc_iomux_set_pad(MX51_PIN_EIM_D16, PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+
+ /* i2c1 SCL */
+ mxc_request_iomux(MX51_PIN_EIM_D19,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH1);
+ mxc_iomux_set_pad(MX51_PIN_EIM_D19, PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+
+ /* i2c2 SDA */
+ mxc_request_iomux(MX51_PIN_KEY_COL5,
+ IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH1);
+ mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
+ PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+
+ /* i2c2 SCL */
+ mxc_request_iomux(MX51_PIN_KEY_COL4,
+ IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH1);
+ mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
+ PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+
+ /* Drive 26M_OSC_EN line high */
+ mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, PAD_CTL_DRV_HIGH |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_set_gpio_direction(MX51_PIN_DI1_PIN12, 0);
+ mxc_set_gpio_dataout(MX51_PIN_DI1_PIN12, 1);
+
+ /* Drive USB_CLK_EN_B line low */
+ mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_set_gpio_direction(MX51_PIN_EIM_D17, 0);
+ mxc_set_gpio_dataout(MX51_PIN_EIM_D17, 0);
+
+ /* MX51_PIN_EIM_D21 - De-assert USB PHY RESETB */
+ mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_EIM_D21, PAD_CTL_DRV_HIGH |
+ PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_set_gpio_direction(MX51_PIN_EIM_D21, 0);
+ mxc_set_gpio_dataout(MX51_PIN_EIM_D21, 1);
+
+ /* hphone_det_b */
+ mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D14, PAD_CTL_100K_PU);
+ mxc_set_gpio_direction(MX51_PIN_NANDF_D14, 1);
+
+ /* audio_clk_en_b */
+ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_DRV_HIGH |
+ PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_set_gpio_direction(MX51_PIN_CSPI1_RDY, 0);
+ mxc_set_gpio_dataout(MX51_PIN_CSPI1_RDY, 0);
+
+ /* power key */
+ mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_EIM_A27, PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_NONE);
+ mxc_set_gpio_direction(MX51_PIN_EIM_A27, 1);
+ }
+
/* Deassert VGA reset to free i2c bus */
mxc_set_gpio_direction(MX51_PIN_EIM_A19, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_A19, 1);
+
+ /* LCD related gpio */
+ mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0);
}
+
+/* workaround for ecspi chipselect pin may not keep correct level when idle */
+void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status,
+ int chipselect)
+{
+ switch (cspi_mode) {
+ case 1:
+ switch (chipselect) {
+ case 0x1:
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0,
+ IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
+ PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ break;
+ case 0x2:
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0,
+ IOMUX_CONFIG_GPIO);
+ mxc_set_gpio_direction(MX51_PIN_CSPI1_SS0, 0);
+ mxc_set_gpio_dataout(MX51_PIN_CSPI1_SS0, 1 & (~status));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+}
+EXPORT_SYMBOL(mx51_babbage_gpio_spi_chipselect_active);
+
+void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+ int chipselect)
+{
+ switch (cspi_mode) {
+ case 1:
+ switch (chipselect) {
+ case 0x1:
+ mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0,
+ IOMUX_CONFIG_GPIO);
+ mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
+ break;
+ case 0x2:
+ mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+}
+EXPORT_SYMBOL(mx51_babbage_gpio_spi_chipselect_inactive);
+
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index de587aa..f7687f7 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -82,9 +82,14 @@ static inline int type## _rev (int rev) \
#ifdef CONFIG_ARCH_MX51
# include <mach/mx51.h>
# define cpu_is_mx51() (1)
+#define board_is_mx51(rev) ((system_rev & rev) ? 1 : 0)
+/* BB25:Bit8 is set to 1, BB20: Bit8 is set to 0 */
+#define board_is_babbage_2_5() ((system_rev & 0x1FF) >> 8)
#else
# define cpu_is_mx51() (0)
-#endif /* CONFIG_ARCh_MX51 */
+#define board_is_mx51(rev) (0)
+#define board_is_babbage_2_5() (0)
+#endif
#ifdef CONFIG_ARCH_MX21
#include <mach/mx21.h>
--
1.6.3.3
--- manjo
More information about the kernel-team
mailing list