[PATCH 121/133] [Jaunty SRU] ARM.imx51 Freescale:ENGR00112918-1: Add support for SW controlled frequency scaling.
Brad Figg
brad.figg at canonical.com
Thu Jul 9 16:49:51 UTC 2009
Add 3 working points for AHB frequencies: 24Mhz, 83.3MHz and 133MHz.
The switching between these modes is done dynamically based on what modules
are active.
Also changed NAND to work in asymmetric mode since in symmetric mode, NFC does
not work correctly when its clocks are changed dynamically.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan at freescale.com>
Signed-off-by: Brad Figg <brad.figg at canonical.com>
---
arch/arm/plat-mxc/clock.c | 14 +++++++++++++-
arch/arm/plat-mxc/cpufreq.c | 19 +++++++++----------
arch/arm/plat-mxc/dvfs_core.c | 17 +++++++----------
arch/arm/plat-mxc/include/mach/clock.h | 6 ++++--
drivers/mtd/nand/mxc_nd2.c | 3 ++-
5 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index c15386c..c4cd7dd 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -43,6 +43,8 @@
#if (defined(CONFIG_ARCH_MX51) || defined(CONFIG_ARCH_MX37))
extern int dvfs_core_is_active;
+extern int lp_high_freq;
+extern int lp_med_freq;
extern void dvfs_core_set_bus_freq(void);
#else
int dvfs_core_is_active;
@@ -174,7 +176,13 @@ int clk_enable(struct clk *clk)
#if defined(CONFIG_CPU_FREQ)
if (dvfs_core_is_active)
dvfs_core_set_bus_freq();
+#if (defined(CONFIG_ARCH_MX51) || defined(CONFIG_ARCH_MX37))
+ else if ((lp_high_freq == 0 && lp_med_freq == 0) ||
+ (lp_high_freq == 1) ||
+ (lp_high_freq == 0 && lp_med_freq == 1))
+#else
else
+#endif
cpufreq_update_policy(0);
#else
if (dvfs_core_is_active)
@@ -207,8 +215,12 @@ void clk_disable(struct clk *clk)
#if defined(CONFIG_CPU_FREQ)
if (dvfs_core_is_active)
dvfs_core_set_bus_freq();
+#if (defined(CONFIG_ARCH_MX51) || defined(CONFIG_ARCH_MX37))
+ else if (lp_high_freq == 0)
+#else
else
- cpufreq_update_policy(0);
+#endif
+ cpufreq_update_policy(0);
#else
if (dvfs_core_is_active)
dvfs_core_set_bus_freq();
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 9ebc5b0..855ce8c 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -50,8 +50,9 @@ extern int high_bus_freq_mode;
extern int dvfs_core_is_active;
extern int cpu_wp_nr;
extern char *gp_reg_id;
+
extern int set_low_bus_freq(void);
-extern int set_high_bus_freq(void);
+extern int set_high_bus_freq(int high_bus_speed);
extern int low_freq_bus_used(void);
#ifdef CONFIG_ARCH_MX51
extern struct cpu_wp *(*get_cpu_wp)(int *wp);
@@ -170,9 +171,10 @@ static int mxc_set_target(struct cpufreq_policy *policy,
freqs.cpu = 0;
freqs.flags = 0;
- if ((freqs.old == freqs.new) && (freqs.new != cpu_freq_khz_min))
+ if ((freqs.old == freqs.new) && (freqs.new != cpu_freq_khz_min)) {
+ set_high_bus_freq(0);
return 0;
-
+ }
low_freq_bus_ready = low_freq_bus_used();
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
@@ -184,14 +186,12 @@ static int mxc_set_target(struct cpufreq_policy *policy,
if (!dvfs_core_is_active)
ret = set_cpu_freq(freq_Hz);
} else {
- if (!high_bus_freq_mode)
- set_high_bus_freq();
-
+ set_high_bus_freq(0);
if (!dvfs_core_is_active)
ret = set_cpu_freq(freq_Hz);
if (low_bus_freq_mode) {
if (ret == 0)
- set_high_bus_freq();
+ set_high_bus_freq(0);
}
}
}
@@ -277,9 +277,8 @@ static int mxc_cpufreq_driver_exit(struct cpufreq_policy *policy)
/* Reset CPU to 665MHz */
if (!dvfs_core_is_active)
set_cpu_freq(arm_normal_clk);
-
- if (low_bus_freq_mode)
- set_high_bus_freq();
+ if (!high_bus_freq_mode)
+ set_high_bus_freq(0);
clk_put(cpu_clk);
regulator_put(gp_regulator);
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index d34ce60..6ec6f0a 100644
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -124,7 +124,7 @@ enum {
extern int low_bus_freq_mode;
extern int high_bus_freq_mode;
extern int set_low_bus_freq(void);
-extern int set_high_bus_freq(void);
+extern int set_high_bus_freq(int high_bus_speed);
extern int low_freq_bus_used(void);
DEFINE_SPINLOCK(mxc_dvfs_core_lock);
@@ -145,10 +145,8 @@ void dvfs_core_set_bus_freq(void)
if ((curr_wp == dvfs_data->num_wp - 1) && (!low_bus_freq_mode)
&& (low_freq_bus_ready))
set_low_bus_freq();
- else if ((curr_wp == dvfs_data->num_wp - 1) && (low_bus_freq_mode)
- && (!low_freq_bus_ready))
- set_high_bus_freq();
-
+ else if (!low_freq_bus_ready)
+ set_high_bus_freq(0);
/* Enable DVFS interrupt */
/* FSVAIM=0 */
reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
@@ -380,13 +378,13 @@ static void dvfs_core_workqueue_handler(struct work_struct *work)
ret = set_cpu_freq(curr_wp);
} else {
if (!high_bus_freq_mode)
- set_high_bus_freq();
+ set_high_bus_freq(0);
ret = set_cpu_freq(curr_wp);
if (low_bus_freq_mode) {
if (ret == 0)
- set_high_bus_freq();
+ set_high_bus_freq(0);
}
}
@@ -435,11 +433,10 @@ static void stop_dvfs(void)
spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
curr_wp = 0;
+ if (!high_bus_freq_mode)
+ set_high_bus_freq(1);
curr_cpu = clk_get_rate(cpu_clk);
if (curr_cpu != cpu_wp_tbl[curr_wp].cpu_rate) {
- if (!high_bus_freq_mode)
- set_high_bus_freq();
-
set_cpu_freq(curr_wp);
#if defined(CONFIG_CPU_FREQ)
if (cpufreq_trig_needed == 1) {
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index abcfe7d..2086701 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel at pengutronix.de
*
* This program is free software; you can redistribute it and/or
@@ -73,6 +73,8 @@ int clk_set_pll_dither(struct clk *clk, unsigned int pll_ppm);
#define ALWAYS_ENABLED (1 << 1) /* Clock cannot be disabled */
#define RATE_FIXED (1 << 2) /* Fixed clock rate */
#define CPU_FREQ_TRIG_UPDATE (1 << 3) /* CPUFREQ trig update */
-
+#define AHB_HIGH_SET_POINT (1 << 4) /* Requires max AHB clock */
+#define AHB_MED_SET_POINT (1 << 5) /* Requires med AHB clock */
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/drivers/mtd/nand/mxc_nd2.c b/drivers/mtd/nand/mxc_nd2.c
index 1b7c910..6bfcb2b 100644
--- a/drivers/mtd/nand/mxc_nd2.c
+++ b/drivers/mtd/nand/mxc_nd2.c
@@ -1130,11 +1130,12 @@ static void mxc_nfc_init(void)
/* Unlock Block Command for given address range */
raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC);
+#ifndef CONFIG_ARCH_MX51
/* Enable symetric mode by default except mx37TO1.0 */
if (!(cpu_is_mx37_rev(CHIP_REV_1_0) == 1))
raw_write(raw_read(REG_NFC_ONE_CYCLE) |
NFC_ONE_CYCLE, REG_NFC_ONE_CYCLE);
-
+#endif
}
static int mxc_alloc_buf(void)
--
1.6.0.4
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