[PATCH 43/133] [Jaunty SRU] ARM.imx51 Freescale:ENGR00111499 mx51:GPU 2D Clock Support

[Brad Figg]

From: Wu Guoxing <b02248 at freescale.com>

Clock Support For the Z160 OpenVG module on mx51

Signed-off-by: Wu Guoxing <b02248 at freescale.com>
Signed-off-by: Brad Figg <brad.figg at canonical.com>
---
 arch/arm/mach-mx51/clock.c    |   24 ++++++++++++++++++++++++
 arch/arm/mach-mx51/crm_regs.h |    5 ++++-
 2 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx51/clock.c b/arch/arm/mach-mx51/clock.c
index 878d413..9d59576 100644
--- a/arch/arm/mach-mx51/clock.c
+++ b/arch/arm/mach-mx51/clock.c
@@ -2730,6 +2730,29 @@ static struct clk emi_garb_clk = {
 	.disable = _clk_disable,
 };
 
+static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+	reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+static struct clk gpu2d_clk = {
+	.name = "gpu2d_clk",
+	.parent = &axi_a_clk,
+	.set_parent = _clk_gpu2d_set_parent,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGR6_CG7_OFFSET,
+	.disable = _clk_disable,
+};
+
 static struct clk *mxc_clks[] = {
 	&osc_clk,
 	&ckih_clk,
@@ -2853,6 +2876,7 @@ static struct clk *mxc_clks[] = {
 	&garb_clk,
 	&emi_garb_clk,
 	&ddr_hf_clk,
+	&gpu2d_clk,
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx51/crm_regs.h b/arch/arm/mach-mx51/crm_regs.h
index 9bc5122..0427991 100644
--- a/arch/arm/mach-mx51/crm_regs.h
+++ b/arch/arm/mach-mx51/crm_regs.h
@@ -186,6 +186,8 @@
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		(4)
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET        (14)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK      (0x3 << 14)
 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
 
@@ -565,8 +567,9 @@
 #define MXC_CCM_CCGR5_CG2_MASK			(0x3 << 4)
 #define MXC_CCM_CCGR5_CG1_OFFSET			2
 #define MXC_CCM_CCGR5_CG0_OFFSET			0
+#define MXC_CCM_CCGR6_CG7_OFFSET            14
+#define MXC_CCM_CCGR6_CG7_MASK          (0x3 << 14)
 #define MXC_CCM_CCGR6_CG6_OFFSET			12
-
 #define MXC_CCM_CCGR6_CG6_MASK			(0x3 << 12)
 #define MXC_CCM_CCGR6_CG5_OFFSET			10
 #define MXC_CCM_CCGR6_CG5_MASK			(0x3 << 10)
-- 
1.6.0.4