Hardy proposed 2.6.24-20-generic kernel will not boot

[Alok Kataria]

On Fri, 2008-07-25 at 15:34 -0700, Alok Kataria wrote:
> On Fri, 2008-07-25 at 14:36 -0700, Tim Gardner wrote:
> > Alok,
> > 
> > Have a look at LP Bugs #251344 and #251379
> > 
> > https://bugs.launchpad.net/bugs/251344
> > https://bugs.launchpad.net/bugs/251379
> > 
> > The CPUID patch set is the most likely culprit. Any thoughts?
> 
> Can you try this patch, i don't see the problem on any of the cpu's that
> i have here. 
> 
> --
> Fix for processors which don't support SSE instructions

Actually the commit message is wrong, it should be SSE2.

Searching through the mainline trees git logs, i found this

commit aa6299926950c8dfe2fea638276cad6def092bc9
Author: Ingo Molnar <mingo at elte.hu>
Date:   Fri Feb 1 23:45:18 2008 +0100

    x86: fix bootup crash in native_read_tsc()
    
    fix bootup crash in native_read_tsc() that was reported on an Athlon-XP
    and bisected. The correct feature boundary for X86_FEATURE_MFENCE_RDTSC
    is not XMM but XMM2.


So the patch that i sent earlier should surely fix the problem. 
> 
> From: Alok N Kataria <akataria at vmware.com>
> 
> 
> ---
> 
>  arch/x86/kernel/cpu/amd.c   |    2 +-
>  arch/x86/kernel/cpu/intel.c |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> 
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index aaa8101..6558ce8 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -302,7 +302,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
>  	if (c->x86 < 6)
>  		clear_bit(X86_FEATURE_MCE, c->x86_capability);
>  
> -	if (cpu_has_xmm)
> +	if (cpu_has_xmm2)
>  		set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
>  }
>  
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 161bbc0..62e5a4b 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -201,7 +201,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
>  	}
>  #endif
>  
> -	if (cpu_has_xmm)
> +	if (cpu_has_xmm2)
>  		set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
>  	if (c->x86 == 15) {
>  		set_bit(X86_FEATURE_P4, c->x86_capability);
> 
> 
> > 
> > I don't have programmer references for all of these CPUs, though I
> > suppose I might be able to find them on-line.
> > 
> > rtg
> > --
> > Tim Gardner tim.gardner at canonical.com