ACK: [PATCH 03/10] cpu/msr: move TSC_ADJUST (3bh) to IA32_MSRs
Colin Ian King
colin.king at canonical.com
Wed Jul 24 15:03:42 UTC 2019
On 11/07/2019 18:46, Alex Hung wrote:
> This is an "architectural MSR" in Table 2-2 in Intel's software
> developer's manual
>
> Signed-off-by: Alex Hung <alex.hung at canonical.com>
> ---
> src/cpu/msr/msr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 8972a161..43090e5d 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -345,6 +345,7 @@ static const msr_info IA32_MSRs[] = {
> { "PLATFORM_ID", 0x00000017, 0x001c000000000000ULL, NULL },
> { "APIC_BASE", 0x0000001b, 0xfffffffffffffeffULL, NULL },
> { "FEATURE_CONTROL", 0x0000003a, 0x000000000016ff07ULL, NULL },
> + { "TSC_ADJUST", 0x0000003b, 0xffffffffffffffffULL, NULL },
> { "BIOS_SIGN_ID", 0x0000008b, 0xffffffff00000000ULL, NULL },
> { "MTRRCAP", 0x000000fe, 0x0000000000000fffULL, NULL },
> /*
> @@ -644,7 +645,6 @@ static const msr_info IA32_ivybridge_ep_MSRs[] = {
>
> static const msr_info IA32_haswell_MSRs[] = {
> { "MSR_PLATFORM_INFO", 0x000000ce, 0x00ffff073000ff00ULL, NULL },
> - { "IA32_TSC_ADJUST", 0x0000003b, 0xffffffffffffffffULL, NULL },
> { "IA32_PERFEVTSEL0", 0x00000186, 0x00000000ffffffffULL, NULL },
> { "IA32_PERFEVTSEL1", 0x00000187, 0x00000000ffffffffULL, NULL },
> { "IA32_PERFEVTSEL2", 0x00000188, 0x00000000ffffffffULL, NULL },
>
Acked-by: Colin Ian King <colin.king at canonical.com>
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