ACK: [PATCH 4/5] cpu/msr: add MSR_BBL_CR_CTL3 to IA32_silvermont_MSRs

[ivanhu]

On 7/12/19 1:08 PM, Alex Hung wrote:
> BIT definition is as below:
> 
> 0	L2 Hardware Enabled (RO)
> 7:1	Reserved
> 8	L2 Enabled (R/W)
> 22:9	Reserved
> 23	L2 Not Present (RO)
> 63:24	Reserved
> 
> Signed-off-by: Alex Hung <alex.hung at canonical.com>
> ---
>   src/cpu/msr/msr.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index f08dac65..daa75d57 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -482,6 +482,7 @@ static const msr_info IA32_atom_MSRs[] = {
>   
>   static const msr_info IA32_silvermont_MSRs[] = {
>   	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
> +	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>   	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
>   	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
>   	{ NULL,				0x00000000,	0, NULL },
> 

Acked-by: Ivan Hu <ivan.hu at canonical.com>