[PATCH] cpu: msr: change SMRR_PHYSBASE from 8MB boundary to 4KB boundary

[Alex Hung]

According to a patch to tianocore [1], the base alignment should
be 4KB instead of 8MB.  It also meets the observation that many
recent systems do not have 8MB alignment.

[1] https://sourceforge.net/p/tianocore/edk2/ci/4be1fbc287a2972a0cb420bc3a85372426c588b5/

Signed-off-by: Alex Hung <alex.hung at canonical.com>
---
 src/cpu/msr/msr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 54ed5a5..22dfb29 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -213,9 +213,9 @@ static int msr_smrr(fwts_framework *fw)
 			if (fwts_cpu_readmsr(0, 0x1f2, &val) == FWTS_OK) {
 				uint64_t physbase = val & 0xfffff000;
 				uint64_t type = val & 7;
-				if ((physbase & 0x7fffff) != 0)
-					fwts_failed(fw, LOG_LEVEL_HIGH, "MSRSMRR_PHYSBASE8MBBoundary",
-						"SMRR: SMRR_PHYSBASE is NOT on an 8MB boundary: %" PRIx64 ".",
+				if ((physbase & 0xfff) != 0)
+					fwts_failed(fw, LOG_LEVEL_HIGH, "MSRSMRR_PHYSBASE4KBBoundary",
+						"SMRR: SMRR_PHYSBASE is NOT on a 4KB boundary: %" PRIx64 ".",
 						physbase);
 				if (type != 6)
 					fwts_failed(fw, LOG_LEVEL_HIGH, "MSRSMRR_TYPE",
-- 
2.7.4