PCI config space sanity checking

[Colin Ian King]

On 02/02/12 13:09, Alex Hung wrote:
> On 02/02/2012 07:57 PM, Colin Ian King wrote:
>> On 02/02/12 03:53, Alex Hung wrote:
>>> The below is a fragment of a result from Intel's Selftest utility.
>>
>> Oh, I don't know about Selftest - where can I get that from? - and
>> what can it do? Is it another tool that we should be using on projects
>> by default to catch issues?
> It can be downloaded from Intel IBL, but an Intel account is needed. It
> only checks the registers in PCI(e) configuration space, CPU MSR or in
> memory space, based on Intel's recommendation. However, it only runs on
> Windows as far as I am aware of.
>
> AMD has a similar utility (called BTS - BIOS Test Suite?).
>>
>>>
>>> - This particular version checks for 12352 settings with Pantherpoint
>>> (PCH with Ivy Bridge), and it is based on BIOS Writer Guide 0.9.
>>>
>>> Stats : Total:12352 Error:64 Warn:55
>>> *********************************************************************************
>>>
>>>
>>> Pantherpoint BIOS Spec 0.9
>>> BWG Version - 0.9
>>>
>>> - It suggests that SSS needs to be enabled but BIOS disables it.
>>> Actual Expected
>>> ---------------------------------------------------------------------------------
>>>
>>>
>>> AHCI Generic Host Control Registers
>>> ---------------------------------------------------------------------------------
>>>
>>>
>>> 00h CAP - Host Capabilities Register
>>> E [27] Supports Staggered Spin-up (SSS) 0x0 0x1
>>> See BIOS Spec 14.1.4 Initialize Registers in AHCI Memory-Mapped Space
>>> Attribute: R/WO
>>> Default: 1
>>> Indicates whether the SATA controller supports staggered spin-up on its
>>> ports, for use in balancing power spikes. This value is loaded by
>>> platform BIOS prior to OS initialization.
>>> 0 = Staggered spin-up not supported.
>>> 1 = Staggered spin-up supported.
>>>
>>> - It shows pass if BIOS sets it right
>>> PASS [4] SMI_LOCK 0x1 0x1
>>> See BIOS Spec 3.6 Flash Security Recommendation-- This recommendation is
>>> only for production BIOS
>>> Attribute: R/WO
>>> Default: 0
>>> When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0)
>>> will have no effect.
>>> Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no
>>> effect (i.e., once set, this bit can only be cleared by PLTRST#).
>>>
>>> - It also shows warning, i.e. when ASPM is not enabled (but this depends
>>> on the attached device).
>>> E8h PECR1 - PCI Express* Configuration Register 1
>>> W [1] PECR1 Field 2 0x0 0x1
>>> Both L0s and L1 Entry Supported. This bit should be set to 1b
>>>
>>
>>> However, this utility only checks registers from CPU or chipset. No ACPI
>>> tables or any other interfaces are analyzed - that's where our fwts
>>> helps. ;-)
>>
>> Indeed :-)
>>
>> So do you think we should realistically add BIOS configured PCI config
>> space checks into fwts as valuable set of tests - or does Selftest
>> cover enough of what we need to check? Perhaps this is up for
>> Precise+1 discussion at UDS
>>
>> Colin
> Agreed. It is a good idea to take a closer look at selftest and worth of
> a good discussion.

Can we put it down as an action point:
	* Investigate features of selftest with possibility of adding these 
type of tests to fwts

..and have the list of features ready for discussion at UDS?

Colin
	

>>

>>>
>>> On 02/01/2012 05:17 PM, Alex Hung wrote:
>>>> On 02/01/2012 12:54 AM, Colin Ian King wrote:
>>>>> Hi there,
>>>>>
>>>>> While discussing some boot speed issues with the kernel with Andy
>>>>> Whitcroft we spotted that that the PCI config space is being set up
>>>>> by the BIOS and this can be sub-optimally configuring things like the
>>>>> SATA capabilities.
>>>>>
>>>>> For example, bit 27 in HBA Capabilities for SATA devices controls the
>>>>> "Staggered Spin-up (SSS)" setting - this really makes sense on
>>>>> servers and hence should be set to zero for netbooks, laptops etc.
>>>>> However, we observed it being incorrectly set on particular platform
>>>>> which can only have one drive in it, so SSS makes no sense.
>>>>>
>>>> SSS looks very familiar. I recall that Intel's BIOS utility (selfcheck
>>>> or selftest for Windows) checks this bit and it suggests a setting (I
>>>> don't remember whether it was 1 or 0).
>>>>
>>>> PS. Both Intel and AMD also have utilities that checks hardware
>>>> registers - thought they make mistakes too.
>>>>
>>>> I think it is a good idea to check hardware configuration but we will
>>>> need to be careful. If fwts suggest different configuration from
>>>> hardware vendors (i.e. Intel, AMD and nVidia), it will cause confusion.
>>>>
>>>>> So, perhaps we should add this to the next round of fwts blueprints -
>>>>> check for incorrect or sub-optimal incorrectly configured PCI config
>>>>> space settings for wide range of devices.
>>>>>
>>>>> Any thoughts?
>>>>>
>>>>> Colin
>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>
>>>
>>
>