[PATCH] msr: remove the IA32_A_PMC0-3 and IA32_TSC_AUX from cosistent test

[Ivan Hu]

checking from Intel 64 and IA32 software architectures develope manual,
the Scope of these MSRs is Thread, it means this bit field must be
programmed on each logical processor independently.

Signed-off-by: Ivan Hu <ivan.hu at canonical.com>
---
 src/cpu/msr/msr.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 5de27a7..0a8cf2c 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -423,10 +423,6 @@ static msr_info IA32_MSRs[] = {
 	{ "VMX_TRUE_EXIT_CTLS",	0x0000048f,	0, ~0, NULL },
 	{ "VMX_TRUE_ENTRY_CTLS",0x00000490,	0, ~0, NULL },
 
-	{ "A_PMC0",		0x000004c1,	0, ~0, NULL },
-	{ "A_PMC1",		0x000004c2,	0, ~0, NULL },
-	{ "A_PMC2",		0x000004c3,	0, ~0, NULL },
-	{ "A_PMC3",		0x000004c4,	0, ~0, NULL },
 	{ "A_PMC4",		0x000004c5,	0, ~0, NULL },
 	{ "A_PMC5",		0x000004c6,	0, ~0, NULL },
 	{ "A_PMC6",		0x000004c7,	0, ~0, NULL },
@@ -439,7 +435,6 @@ static msr_info IA32_MSRs[] = {
 	//{ "FS_BASE",		0xc0000100,	0, ~0, NULL },
 	//{ "GS_BASE",		0xc0000101, 	0, ~0, NULL },
 	{ "KERNEL_GS_BASE",	0xc0000102, 	0, ~0, NULL },
-	{ "TSC_AUX",		0xc0000103, 	0, 0xffffffffULL, NULL },
 	{ NULL,			0x00000000,	0, 0 , NULL },
 };
 
-- 
1.7.9.5