[ubuntu/bionic-proposed] linux-azure_4.15.0-1021.21_amd64.tar.gz - (Accepted)
Stefan Bader
stefan.bader at canonical.com
Tue Aug 14 17:16:57 UTC 2018
linux-azure (4.15.0-1021.21) bionic; urgency=medium
[ Ubuntu: 4.15.0-32.34 ]
* CVE-2018-5391
- Revert "net: increase fragment memory usage limits"
* CVE-2018-3620 // CVE-2018-3646
- x86/Centaur: Initialize supported CPU features properly
- x86/Centaur: Report correct CPU/cache topology
- x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be present
- perf/events/amd/uncore: Fix amd_uncore_llc ID to use pre-defined cpu_llc_id
- x86/CPU: Rename intel_cacheinfo.c to cacheinfo.c
- x86/CPU/AMD: Calculate last level cache ID from number of sharing threads
- x86/CPU: Modify detect_extended_topology() to return result
- x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available
- x86/CPU: Move cpu local function declarations to local header
- x86/CPU: Make intel_num_cpu_cores() generic
- x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()
- x86/CPU: Move x86_cpuinfo::x86_max_cores assignment to
detect_num_cpu_cores()
- x86/CPU/AMD: Fix LLC ID bit-shift calculation
- x86/mm: Factor out pageattr _PAGE_GLOBAL setting
- x86/mm: Undo double _PAGE_PSE clearing
- x86/mm: Introduce "default" kernel PTE mask
- x86/espfix: Document use of _PAGE_GLOBAL
- x86/mm: Do not auto-massage page protections
- x86/mm: Remove extra filtering in pageattr code
- x86/mm: Comment _PAGE_GLOBAL mystery
- x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
- x86/ldt: Fix support_pte_mask filtering in map_ldt_struct()
- x86/power/64: Fix page-table setup for temporary text mapping
- x86/pti: Filter at vma->vm_page_prot population
- x86/boot/64/clang: Use fixup_pointer() to access '__supported_pte_mask'
- x86/speculation/l1tf: Increase 32bit PAE __PHYSICAL_PAGE_SHIFT
- x86/speculation/l1tf: Change order of offset/type in swap entry
- x86/speculation/l1tf: Protect swap entries against L1TF
- x86/speculation/l1tf: Protect PROT_NONE PTEs against speculation
- x86/speculation/l1tf: Make sure the first page is always reserved
- x86/speculation/l1tf: Add sysfs reporting for l1tf
- x86/speculation/l1tf: Disallow non privileged high MMIO PROT_NONE mappings
- x86/speculation/l1tf: Limit swap file size to MAX_PA/2
- x86/bugs: Move the l1tf function and define pr_fmt properly
- sched/smt: Update sched_smt_present at runtime
- x86/smp: Provide topology_is_primary_thread()
- x86/topology: Provide topology_smt_supported()
- cpu/hotplug: Make bringup/teardown of smp threads symmetric
- cpu/hotplug: Split do_cpu_down()
- cpu/hotplug: Provide knobs to control SMT
- x86/cpu: Remove the pointless CPU printout
- x86/cpu/AMD: Remove the pointless detect_ht() call
- x86/cpu/common: Provide detect_ht_early()
- x86/cpu/topology: Provide detect_extended_topology_early()
- x86/cpu/intel: Evaluate smp_num_siblings early
- x86/CPU/AMD: Do not check CPUID max ext level before parsing SMP info
- x86/cpu/AMD: Evaluate smp_num_siblings early
- x86/apic: Ignore secondary threads if nosmt=force
- x86/speculation/l1tf: Extend 64bit swap file size limit
- x86/cpufeatures: Add detection of L1D cache flush support.
- x86/CPU/AMD: Move TOPOEXT reenablement before reading smp_num_siblings
- x86/speculation/l1tf: Protect PAE swap entries against L1TF
- x86/speculation/l1tf: Fix up pte->pfn conversion for PAE
- Revert "x86/apic: Ignore secondary threads if nosmt=force"
- cpu/hotplug: Boot HT siblings at least once
- x86/KVM: Warn user if KVM is loaded SMT and L1TF CPU bug being present
- x86/KVM/VMX: Add module argument for L1TF mitigation
- x86/KVM/VMX: Add L1D flush algorithm
- x86/KVM/VMX: Add L1D MSR based flush
- x86/KVM/VMX: Add L1D flush logic
- x86/KVM/VMX: Split the VMX MSR LOAD structures to have an host/guest numbers
- x86/KVM/VMX: Add find_msr() helper function
- x86/KVM/VMX: Separate the VMX AUTOLOAD guest/host number accounting
- x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRs
- x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if required
- cpu/hotplug: Online siblings when SMT control is turned on
- x86/litf: Introduce vmx status variable
- x86/kvm: Drop L1TF MSR list approach
- x86/l1tf: Handle EPT disabled state proper
- x86/kvm: Move l1tf setup function
- x86/kvm: Add static key for flush always
- x86/kvm: Serialize L1D flush parameter setter
- x86/kvm: Allow runtime control of L1D flush
- cpu/hotplug: Expose SMT control init function
- cpu/hotplug: Set CPU_SMT_NOT_SUPPORTED early
- x86/bugs, kvm: Introduce boot-time control of L1TF mitigations
- Documentation: Add section about CPU vulnerabilities
- x86/speculation/l1tf: Unbreak !__HAVE_ARCH_PFN_MODIFY_ALLOWED architectures
- x86/KVM/VMX: Initialize the vmx_l1d_flush_pages' content
- Documentation/l1tf: Fix typos
- cpu/hotplug: detect SMT disabled by BIOS
- x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush()
- x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond'
- x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush()
- x86/irq: Demote irq_cpustat_t::__softirq_pending to u16
- x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1d
- x86: Don't include linux/irq.h from asm/hardirq.h
- x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1d
- x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr()
- Documentation/l1tf: Remove Yonah processors from not vulnerable list
- x86/speculation: Simplify sysfs report of VMX L1TF vulnerability
- x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
- KVM: x86: Add a framework for supporting MSR-based features
- KVM: X86: Introduce kvm_get_msr_feature()
- KVM: VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR
- KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentry
- cpu/hotplug: Fix SMT supported evaluation
- x86/speculation/l1tf: Invert all not present mappings
- x86/speculation/l1tf: Make pmd/pud_mknotpresent() invert
- x86/mm/pat: Make set_memory_np() L1TF safe
Date: Fri, 10 Aug 2018 11:22:51 +0200
Changed-By: Stefan Bader <stefan.bader at canonical.com>
Maintainer: Launchpad Build Daemon <buildd at lgw01-amd64-035.buildd>
-------------- next part --------------
Format: 1.8
Date: Fri, 10 Aug 2018 11:22:51 +0200
Source: linux-azure
Binary: linux-azure-headers-4.15.0-1021 linux-azure-tools-4.15.0-1021 linux-azure-cloud-tools-4.15.0-1021 linux-image-unsigned-4.15.0-1021-azure linux-modules-4.15.0-1021-azure linux-modules-extra-4.15.0-1021-azure linux-headers-4.15.0-1021-azure linux-image-unsigned-4.15.0-1021-azure-dbgsym linux-tools-4.15.0-1021-azure linux-cloud-tools-4.15.0-1021-azure linux-udebs-azure
Architecture: amd64 all amd64_translations
Version: 4.15.0-1021.21
Distribution: bionic
Urgency: medium
Maintainer: Launchpad Build Daemon <buildd at lgw01-amd64-035.buildd>
Changed-By: Stefan Bader <stefan.bader at canonical.com>
Description:
linux-azure-cloud-tools-4.15.0-1021 - Linux kernel version specific cloud tools for version 4.15.0-1021
linux-azure-headers-4.15.0-1021 - Header files related to Linux kernel version 4.15.0
linux-azure-tools-4.15.0-1021 - Linux kernel version specific tools for version 4.15.0-1021
linux-cloud-tools-4.15.0-1021-azure - Linux kernel version specific cloud tools for version 4.15.0-1021
linux-headers-4.15.0-1021-azure - Linux kernel headers for version 4.15.0 on 64 bit x86 SMP
linux-image-unsigned-4.15.0-1021-azure - Linux kernel image for version 4.15.0 on 64 bit x86 SMP
linux-image-unsigned-4.15.0-1021-azure-dbgsym - Linux kernel debug image for version 4.15.0 on 64 bit x86 SMP
linux-modules-4.15.0-1021-azure - Linux kernel extra modules for version 4.15.0 on 64 bit x86 SMP
linux-modules-extra-4.15.0-1021-azure - Linux kernel extra modules for version 4.15.0 on 64 bit x86 SMP
linux-tools-4.15.0-1021-azure - Linux kernel version specific tools for version 4.15.0-1021
linux-udebs-azure - Metapackage depending on kernel udebs (udeb)
Changes:
linux-azure (4.15.0-1021.21) bionic; urgency=medium
.
[ Ubuntu: 4.15.0-32.34 ]
.
* CVE-2018-5391
- Revert "net: increase fragment memory usage limits"
* CVE-2018-3620 // CVE-2018-3646
- x86/Centaur: Initialize supported CPU features properly
- x86/Centaur: Report correct CPU/cache topology
- x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be present
- perf/events/amd/uncore: Fix amd_uncore_llc ID to use pre-defined cpu_llc_id
- x86/CPU: Rename intel_cacheinfo.c to cacheinfo.c
- x86/CPU/AMD: Calculate last level cache ID from number of sharing threads
- x86/CPU: Modify detect_extended_topology() to return result
- x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available
- x86/CPU: Move cpu local function declarations to local header
- x86/CPU: Make intel_num_cpu_cores() generic
- x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()
- x86/CPU: Move x86_cpuinfo::x86_max_cores assignment to
detect_num_cpu_cores()
- x86/CPU/AMD: Fix LLC ID bit-shift calculation
- x86/mm: Factor out pageattr _PAGE_GLOBAL setting
- x86/mm: Undo double _PAGE_PSE clearing
- x86/mm: Introduce "default" kernel PTE mask
- x86/espfix: Document use of _PAGE_GLOBAL
- x86/mm: Do not auto-massage page protections
- x86/mm: Remove extra filtering in pageattr code
- x86/mm: Comment _PAGE_GLOBAL mystery
- x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
- x86/ldt: Fix support_pte_mask filtering in map_ldt_struct()
- x86/power/64: Fix page-table setup for temporary text mapping
- x86/pti: Filter at vma->vm_page_prot population
- x86/boot/64/clang: Use fixup_pointer() to access '__supported_pte_mask'
- x86/speculation/l1tf: Increase 32bit PAE __PHYSICAL_PAGE_SHIFT
- x86/speculation/l1tf: Change order of offset/type in swap entry
- x86/speculation/l1tf: Protect swap entries against L1TF
- x86/speculation/l1tf: Protect PROT_NONE PTEs against speculation
- x86/speculation/l1tf: Make sure the first page is always reserved
- x86/speculation/l1tf: Add sysfs reporting for l1tf
- x86/speculation/l1tf: Disallow non privileged high MMIO PROT_NONE mappings
- x86/speculation/l1tf: Limit swap file size to MAX_PA/2
- x86/bugs: Move the l1tf function and define pr_fmt properly
- sched/smt: Update sched_smt_present at runtime
- x86/smp: Provide topology_is_primary_thread()
- x86/topology: Provide topology_smt_supported()
- cpu/hotplug: Make bringup/teardown of smp threads symmetric
- cpu/hotplug: Split do_cpu_down()
- cpu/hotplug: Provide knobs to control SMT
- x86/cpu: Remove the pointless CPU printout
- x86/cpu/AMD: Remove the pointless detect_ht() call
- x86/cpu/common: Provide detect_ht_early()
- x86/cpu/topology: Provide detect_extended_topology_early()
- x86/cpu/intel: Evaluate smp_num_siblings early
- x86/CPU/AMD: Do not check CPUID max ext level before parsing SMP info
- x86/cpu/AMD: Evaluate smp_num_siblings early
- x86/apic: Ignore secondary threads if nosmt=force
- x86/speculation/l1tf: Extend 64bit swap file size limit
- x86/cpufeatures: Add detection of L1D cache flush support.
- x86/CPU/AMD: Move TOPOEXT reenablement before reading smp_num_siblings
- x86/speculation/l1tf: Protect PAE swap entries against L1TF
- x86/speculation/l1tf: Fix up pte->pfn conversion for PAE
- Revert "x86/apic: Ignore secondary threads if nosmt=force"
- cpu/hotplug: Boot HT siblings at least once
- x86/KVM: Warn user if KVM is loaded SMT and L1TF CPU bug being present
- x86/KVM/VMX: Add module argument for L1TF mitigation
- x86/KVM/VMX: Add L1D flush algorithm
- x86/KVM/VMX: Add L1D MSR based flush
- x86/KVM/VMX: Add L1D flush logic
- x86/KVM/VMX: Split the VMX MSR LOAD structures to have an host/guest numbers
- x86/KVM/VMX: Add find_msr() helper function
- x86/KVM/VMX: Separate the VMX AUTOLOAD guest/host number accounting
- x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRs
- x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if required
- cpu/hotplug: Online siblings when SMT control is turned on
- x86/litf: Introduce vmx status variable
- x86/kvm: Drop L1TF MSR list approach
- x86/l1tf: Handle EPT disabled state proper
- x86/kvm: Move l1tf setup function
- x86/kvm: Add static key for flush always
- x86/kvm: Serialize L1D flush parameter setter
- x86/kvm: Allow runtime control of L1D flush
- cpu/hotplug: Expose SMT control init function
- cpu/hotplug: Set CPU_SMT_NOT_SUPPORTED early
- x86/bugs, kvm: Introduce boot-time control of L1TF mitigations
- Documentation: Add section about CPU vulnerabilities
- x86/speculation/l1tf: Unbreak !__HAVE_ARCH_PFN_MODIFY_ALLOWED architectures
- x86/KVM/VMX: Initialize the vmx_l1d_flush_pages' content
- Documentation/l1tf: Fix typos
- cpu/hotplug: detect SMT disabled by BIOS
- x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush()
- x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond'
- x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush()
- x86/irq: Demote irq_cpustat_t::__softirq_pending to u16
- x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1d
- x86: Don't include linux/irq.h from asm/hardirq.h
- x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1d
- x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr()
- Documentation/l1tf: Remove Yonah processors from not vulnerable list
- x86/speculation: Simplify sysfs report of VMX L1TF vulnerability
- x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
- KVM: x86: Add a framework for supporting MSR-based features
- KVM: X86: Introduce kvm_get_msr_feature()
- KVM: VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR
- KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentry
- cpu/hotplug: Fix SMT supported evaluation
- x86/speculation/l1tf: Invert all not present mappings
- x86/speculation/l1tf: Make pmd/pud_mknotpresent() invert
- x86/mm/pat: Make set_memory_np() L1TF safe
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